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CHAPTER 15 Interrupt Controller
15.1 Overview of Interrupt Controller
The interrupt controller comprises of the interrupt control register, interrupt priority
decision circuit, interrupt level, and interrupt number generation sections, and controls
interrupt reception and adjustment.
■ Block Diagram of Interrupt Controller
Figure 15.1-1 Block Diagram of Interrupt controller
Notes:
• The DLYI in the figure means the delayed interrupt section. (For details, see "CHAPTER 14 ".)
• INT* is the wake-up signal to the clock control sections during sleep/stop status.
LEVEL4 to 0
OR
LEVEL judgement
ICR00
RI00
VCT5 to 0
(to CPU)
LEVEL,
VECTOR
Generation
VECTOR
judgement
ICR47
RI47
DLYI
DLYIR Q
R-Bus
INT*(C-unit)
Priority judgement