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CHAPTER 6 FG Input
[bit2]:R0FCLR
This is the edge detection flag clear bit during the reel 0 masking.
The read value of this bit is always "1".
[bit1]:R0MTS
This is the reel 0 mask timer status flag.
[bit0]:R0MTCS
This is clock source selection bit of reel 0 mask timer.
■ Reel Input Control Register (RLxDVC)
Figure 6.4-4 Reel input control register (RLxDVC)
[bit7 to 0]:DIV7 to 0
Division control of the drum input and edge detection control are performed by the set value.
0 Clear RL0D flag
1 None
0 Mask released
1 Masking
Selection Clock in fch:@20MHz
0
2
10
/fch (FRC9)
51.2 µs
1
2
14
/fch (FRC13)
819.2 µs
7 6 5 4 3 2 1 0
XXXX XXXX
B
Initial value
bit
DIV7 DIV6 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0
R/W R/W R/W R/W R/W R/W R/W R/W
Access
Set value Division control Edge detection
00
H
None Both edge detection
01
H
1-frequency division
02
H
2-frequency division
03
H
3-frequency division
to to Rising edge detection
FD
H
253-frequency division
FE
H
254-frequency division
FF
H
255-frequency division