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CHAPTER 4 External Bus Interface
stb r0,@r1 // dscr register write
init_amd0 ldi:8 #0x10,r0 // 32-bit bus, 0-wait
ldi:20 #0x620,r1 // amd0 register address setting
stb r0,@r1 // amd0 register write
init_amd1 ldi:8 #0x8a,r0 // time division, 16-bit bus, 2-wait
ldi:20 #0x621,r1 // amd1 register address setting
stb r0,@r1 // amd1 register write
init_amd32 ldi:8 #0x89,r0 // Normal, 32-bit bus, 1-wait
ldi:20 #0x622,r1 // amd32 register address setting
stb r0,@r1 // amd32 register write
init_amd4 ldi:8 #0x88,r0 // DRAM, 16-bit bus
ldi:20 #0x623,r1 // amd4 register address setting
stb r0,@r1 // amd4 register write
init_amd5 ldi:8 #0x88,r0 // DRAM, 16-bit bus
ldi:20 #0x624,r1 // amd5 register address setting
stb r0,@r1 // amd5 register write
init_dmcr4 ldi:20 #0x0c90,r0 // page size=256, Q1/Q4-wait, Page
// 1CAS-2WE, CBR, No parity
ldi:20 #0x62c,r1 // dmcr4 register address setting
sth r0,@r1 // dmcr4 register write
init_dmcr5 ldi:20 #0x10c0,r0 // page size=512, Q1/Q4-wait none, Page
// 2CAS-1WE, CBR, No parity
ldi:20 #0x62e,r1 // dmcr5 register address setting
sth r0,@r1 // dmcr5 register write
init_rfcr ldi:20 #0x0205,r0 // REL=2, R1W/R3W-wait none, refresh, 1/8
ldi:20 #0x626,r1 // rfcr register address setting
sth r0,@r1 // rfcr register write
init_asr ldi:32 #0x0013001,r0 // asr1,amr1 register setting value
ldi:32 #0x0015001,r1 // asr2,amr2 register setting value
ldi:32 #0x0017001,r2 // asr3,amr3 register setting value
ldi:32 #0x0019001,r3 // asr4,amr4 register setting value
ldi:32 #0x001b001,r4 // asr5,amr5 register setting value
ldi:20 #0x60c,r5 // asr1,amr1 register address setting
ldi:20 #0x610,r6 // asr2,amr2 register address setting
ldi:20 #0x614,r7 // asr3,amr3 register address setting
ldi:20 #0x618,r8 // asr4,amr4 register address setting
ldi:20 #0x61C,r9 // asr5,amr5 register address setting
st r0,@r5 // asr1,amr1 register write
st r1,@r6 // asr2,amr2 register write