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The number of cycles taken for reading is 2 cycles per half-word (1 wait).
• Writing command to the flash memory enables the auto algorithm to be initiated. Initiating auto
algorithm enables the flash memory to be erased or written. Refer to "21.4 Flash Memory Auto
Algorithm (Embedded Algorithm TM)" for details of the auto algorithm.
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Restrictions
• The address allocation method and endian type differ from writing the ROM writer.
• Under this mode, reading data of word (32-bit) length is disabled.
• When setting the gear cycle of the CPU system to source oscillation x 1, 1 Wait must be specified by the
Wait control area before setting.
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Auto Algorithm Execute State
When auto algorithm is initiated under CPU programming mode, the auto algorithm operation status can be
identified by the internal ready/busy signal (RDY/BUSYX). This ready/busy signal level can be read as the
"RDY" bit of the flash memory status register.
While the "RDY" bit is "0", writing or erasing is carried out by the auto algorithm, and no new write or
erase commands can be received. Also, data cannot be read form the flash memory address.
The data read while the "RDY" bit is "0" is the hardware sequence flag indicating the flash memory status.
(Refer to "21.5 Auto Algorithm Execute State ■Hardware sequence flag" for details.)
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Interrupt Control
Interrupt request can be generated to the CPU by the exit sequence of the auto algorithm. By doing this, the
end of prolonged auto algorithm sequences can be known immediately.
Auto algorithm exit interrupt is controlled by the "RDYINT" and "INTE" bit of the flash memory status
register.
"RDYINT" bit is the auto algorithm termination interrupt flag. When detecting the rising edge of "0" from
"1" of the internal ready/busy signal (RDY/BUSYX), sets to "1". When the "INTE" bit is "1", if the
"RDYINT" bit is set, an interrupt request is output to the CPU.
Write "0" to the "RDYINT" bit or "INTE" bit to cancel the interrupt request.