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CHAPTER 3 CPU
[bit3, 2]:PCK1, 0
These bits specify the peripheral gear cycle. The bits and the selected cycles have the following
relationship. These bits are initialized by a reset.
[bit0]:CHC
This bit selects whether 1/2 division cycle or PLL/DCC cycle of the oscillation circuit is used as the
basic clock. The setting "1" is the 1/2 division cycle and the setting "0" is the PLL/DCC cycle.
Table 3.12-4 Peripheral machine clock
PCK1 PCK0 CHC
Peripheral machine clock
(source oscillation: input frequency from X0)
0 0 0 Source oscillation × 1
0 1 0 Source oscillation × 1/2
1 0 0 Source oscillation × 1/4
1 1 0 Source oscillation × 1/8
0 0 1 Source oscillation × 1/2
0 1 1 Source oscillation × 1/2 × 1/2
1 0 1 Source oscillation × 1/2 × 1/4
1 1 1 Source oscillation × 1/2 × 1/8 (Initial value)