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CHAPTER 7 FRC Capture
7.2 Register of FRC Capture
This section shows the register configuration/functions of the FRC capture.
■ Capture Input Control Register (CIC1, CIC0)
●
Capture input control register (CIC1)
Figure 7.2-1 Capture input control register (CIC1)
[bit7]:FCIF
It is capture request detection and interrupt request flag.
[bit6]:FCLR
It is capture request detection flag clear bit.
The read value of this bit is always "1".
[bit5]:FCIE
It is interrupt request enable bit.
[bit4, 3]:
It is an unused bit.
[bit2]:EIV2
It is EXI2 input edge detection polarity selection bit.
7 6 5 4 3 2 1 0
X10- -000
B
Initial value
bit
FCIF FCLR FCIE ICR2 ICR1 ICR0
R W R/W R/W R/WR/W
Access
Address: 000064
H
0 No capture request
1 Detect capture request
0 Clear CIF flag.
1 None
0 Interdiction
1 Permission
0 Falling edge detection
1 Rising edge detection