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CHAPTER 5 I/O Port
■ Registers for Port A, B
●
Port A, B data register (PDRA, B)
Figure 5.8-2 Port A data register (PDRA)
Figure 5.8-3 Port B data register (PDRB)
●
Port A, B direction register (DDRA, B)
Figure 5.8-4 Port A direction register (DDRA)
Figure 5.8-5 Port B direction register (DDRB)
●
Port A, B input enable register (PIEA, B)
Figure 5.8-6 Port A input enable register (PIEA)
Figure 5.8-7 Port B input enable register (PIEB)
When the port is used for input functions, input is enabled by setting "1" to the supported bit.
Set "0" for the port is to be used as the analog input.
7 6 5 4 3 2 1 0
XXXX XXXX
B
Initial value
bit
R/W R/W R/W R/W R/W R/W R/W R/W
PDA7 PDA6 PDA5 PDA4 PDA3 PDA2 PDA1 PDA0
Access
Address: 000011
H
7 6 5 4 3 2 1 0
XXXX XXXX
B
Initial value
bit
R/W R/W R/W R/W R/W R/W R/W R/W
PDB7 PDB6 PDB5 PDB4 PDB3 PDB2 PDB1 PDB0
Access
Address: 000010
H
7 6 5 4 3 2 1 0
0000 0000
B
Initial value
bit
WWWWWWWW
DRA7 DRA6 DRA5 DRA4 DRA3 DRA2 DRA1 DRA0
Access
Address: 000019
H
7 6 5 4 3 2 1 0
0000 0000
B
Initial value
bit
WWWWWWWW
DRB7 DRB6 DRB5 DRB4 DRB3 DRB2 DRB1 DRB0
Access
Address: 000018
H
7 6 5 4 3 2 1 0
0000 0000
B
Initial value
bit
WWWWWWWW
PIA7 PIA6 PIA5 PIA4 PIA3 PIA2 PIA1 PIA0
Access
Address: 000021
H
7 6 5 4 3 2 1 0
0000 0000
B
Initial value
bit
WWWWWWWW
PIB7 PIB6 PIB5 PIB4 PIB3 PIB2 PIB1 PIB0
Access
Address: 000020
H