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3.9.5 Operation of EIT
This section explains operation of EIT
■ Operation of EIT
As per the following explanation, the "PC" at the transfer origin indicates the address of the command that
detected each EIT factor.
The "following command address" means that the command that detected EIT is as follows.
• If LDI is 32: PC+6
• If LDI: 20 and COPOP, COPLD, COPST and used: PC+4
• Other instructions: PC+2
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Operation of user interruption/NMI
When a user interrupt or interrupt request of NMI for user is generated, the request is accepted or not is
determined in the following order.
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Right or wrong judgment of interruption demand acceptance
1. The interruption levels of requests that are generated simultaneously are compared, and the one with the
highest level (the smallest numeric value) will be selected. In terms of the levels used for comparisons,
the value retained by the supported ICR is used for mask enable interrupts, and a predetermined constant
is used for NMI.
2. When a number of interrupt requests of the same level are generated, the one with the youngest interrupt
number is selected.
3. Compares the interrupt level with the selected interrupt request with the level mask value determined by
ILM.
When the interrupt level is greater than or equal to the level mask value, the interrupt request is masked
and not accepted.
To (4) at interrupt levels < level mask value.
4. When the selected interruption request is an interruption that can be masked, the interruption request
will be masked and will not be accepted when the I flag is 0. If the I flag is 1, go to 5). When the
selected interrupt request is NMI, go to 5) regardless of the I-flag value.
5. When the above condition occurs, the interrupt request is accepted at the command-processing gap.
When an EIT request is detected, if the user interrupt/NMI request is accepted, the CPU operates as follows
using the interrupt number supporting the accepted interrupt request. ( ) in the [operation] shows the
address which the register indicates.