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4.4 Bus Interface
The bus interface has an follow:
• Normal bus interface
• Time division I/O interface of address and data
• DRAM control interface
These interfaces can only be used in predetermined areas.
■ Bus Interface
Table 4.4-1 shows the correspondence between each chip select area and the usable interface function. The
area mode register (AMD) is specifies which interface is used.
●
Specifying time division I/O
In area 1, the address and data are time division input/output on the bus with the width set by AMD1.
The latch pulse of address is output to the ALE pin.
●
Specifying bus size
A bus width can be specified the area 1 by the register setting.
Table 4.4-1 Each area and usable interface mode
Area
Selectable bus interface
Remark
Normal Bus Time division DRAM
0 - - - The use of the terminal is prohibited.
1 - -
2 to 5 - - - The use of the terminal is prohibited.