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■
Transfer Instruction between Registers
■
Normal Divergence (There is no delay) Instruction
Table E-12 Transfer instruction between registers
Mnemonic Type OP CYCLE NZVC Operation Remark
MOV Rj,Ri
MOV Rs,Ri
MOV Ri,Rs
MOV PS,Ri
MOV Ri,PS
A
A
A
E
E
8B
B7
B3
17-1
07-1
1
1
1
1
c
----
----
----
----
CCCC
Rj
→
Ri
Rs→
Ri
Ri→
Rs
PS
→
Ri
Ri→
PS
Transfer between general purpose register
Rs: special register
*
Rs: special register
*
*: Special register Rs: TBR, RP, USP, SSP, MDH, MDL
Table E-13 Normal divergence (There is no delay) instruction
Mnemonic Type OP CYCLE NZVC Operation Remark
JMP @Ri E 97-0 2 ---- Ri
→
PC
CALL label12
CALL @Ri
F
E
D0
97-1
2
2
----
----
PC+2→
RP,
PC+2+(label12-PC-2)→
PC
PC+2
→
RP,Ri
→
PC
RET E 97-2 2 ---- RP
→
PC Return
INT #u8
INTE
D
E
1F
9F-3
3+3a
3+3a
----
----
SSP-=4,PS→
(SSP),
SSP-=4,PC+2→
(SSP),
0: I flag, 0: S flag
(TBR+0x3FC-u8
×
4)
→
PC
SSP-=4,PS→
(SSP),
SSP-=4,PC+2
→
(SSP),
0→
S Flag,
(TBR+0x3D8) →
PC
for emulator
RETI E 97-3 2+2a CCCC (R15)
→
PC,R15-=4,
(R15) →
PS,R15-=4
BRA label9
BNO label9
BEQ label9
BNE label9
BC label9
BNC label9
BN label9
BP label9
BV label9
BNV label9
BLT label9
BGE label9
BLE label9
BGT label9
BLS label9
BHI label9
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
2
1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
----
----
----
----
----
----
----
----
----
----
----
----
----
----
----
----
PC+2+(label9-PC-2)
→
PC
not diverge
if(Z==1)then
PC+2+(label9-PC-2) →
PC
↑
s/Z==0
↑
s/C==1
↑
s/C==0
↑
s/N==1
↑
s/N==0
↑
s/V==1
↑
s/V==0
↑
s/VxorN==1
↑
s/VxorN==0
↑
s/(VxorN)orZ==1
↑
s/(VxorN)orZ==0
↑
s/CorZ==1
↑
s/CorZ==0