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CHAPTER 3 CPU
[bit0] C: carrying flag
This bit indicates whether or not carry or borrow was generated from the highest bit through the
operation.
Initial state by reset is irregular.
●
System Condition code Register (SCR)
Figure 3.3-10 shows the configuration of the system condition code register (SCR: System Condition Code
Register).
Figure 3.3-10 System condition code register (SCR)
Each bit function of the system condition code register (SCR) is explained as follows.
[bit10, 9] D1, D0: Flag for step division
The middle data of step division execution time is maintained. Do not change while executing the
division processing.
Restart of the step division is guaranteed by saving/returning the PS register value when other processes
are carried out during the step division. Initial state by reset is irregular.
When the DIV0S instruction is executed, the divided and the divisor are referenced and set.
When the DIV0U instruction is executed, the bits clear forcibly.
[bit8] T: step trace trap flag
It is a flag which specifies whether to make the step trace trap effective.
This bit is initialized to "0" by a reset.
The emulator uses the function of the step trace trap. When the emulator is used, it cannot be used in user
program.
Value Function
0 It is indicated that no carry or borrow has occurred.
1 It is indicated that a carry or borrow has occurred.
10 9 8 Initial value
D1 D0 T XX0
H
bit
Value Function
0 Step trace trap invalidity
1
Step trace trap effective
In this case, all NMIs for user and user interrupts will be interrupt disabled.