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6.2 Capstan Input
The capstan input section is comprised of a multiplying circuit, 8-bit programmable
divider, and mask timer. This section explains the operation of each section and control
register.
■ Block Diagram of Capstan Input
Figure 6.2-1 Block Diagram of Capstan Input
■ Register List of Capstan Input
Figure 6.2-2 Register list of Capstan Input
SR
Load (Sync)
Load (Sync)
Write ST
Internal Bus
2 multipli-
cation
CFGD
FCLRCMTSMTCSDUB
CAPC
CAPMTC
00
00
QS
R1
R2
8bit
CAPDVC
2
14
/fch
2
10
/fch
CFG
Programmable devider
(from FRC
FRC9, 13)
START (Mask Enable)
Mask Timer
Mask End
DVCFG Free
(Mask Disable)
RS-FF
DVCFG
(to FRC)
M
P
X
M
P
X
Capstan input control register
Capstan timer control register
Capstan control register
70bit
Address:
000050
H
000051H
000052H
CAPDVC
CAPMTC
CAPC