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■ Reel Control Register (RLC)
Figure 6.4-3 Reel Control Register (RLC)
[bit7]:RL1D
This is the division FG edge detection flag during reel 1 masking.
[bit6]:R1FCLR
This is the edge detection flag clear bit during the reel 1 masking.
The read value of this bit is always "1".
[bit5]:R1MTS
This is the reel 1 mask timer status flag.
[bit4]:R1MTCS
This is clock source selection bit of reel 1 mask timer.
[bit3]:RL0D
This is the division FG edge detection flag during the reel 0 masking.
7 6 5 4 3 2 1 0
X1X0 X1X0
B
Initial value
bit
RL1D R1FCLR R1MTS R1MTCS RL0D R0FCLR R0MTS R0MTCS
RWRR/WRWRR/W
Access
Address: 000057
H
0 Without edge detection
1 With edge detection
0 Clear RL1D flag.
1 None
0 Mask released
1 Masking
Selection Clock in fch:@20MHz
0
2
10
/fch (FRC9)
51.2 µs
1
2
14
/fch (FRC13)
819.2 µs
0 Without edge detection
1 With edge detection