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CONTENTS
CHAPTER 1 Overview of MB91191/MB91192 Series ..................................................... 1
1.1 Feature of MB91191/MB91192 Series ............................................................................................... 2
1.2 Block Diagram of All MB91191/MB91192 Series ............................................................................... 4
1.3 Package Dimension ............................................................................................................................ 5
1.4 Pin Assignment ................................................................................................................................... 7
1.5 Pin Function Description ..................................................................................................................... 9
1.6 I/O Circuit Type ................................................................................................................................. 15
CHAPTER 2 Handling Devices ...................................................................................... 17
2.1 Precautions When Handling Devices ............................................................................................... 18
2.2 Others ............................................................................................................................................... 22
CHAPTER 3 CPU ............................................................................................................ 23
3.1 Memory Space .................................................................................................................................. 24
3.2 CPU Architecture .............................................................................................................................. 26
3.3 Dedicated Registers ......................................................................................................................... 29
3.3.1 Program Status Register (PS) ..................................................................................................... 32
3.4 General-purpose Register ................................................................................................................ 36
3.5 Data Construction ............................................................................................................................. 37
3.6 Word Alignment ................................................................................................................................ 38
3.7 Memory Map ..................................................................................................................................... 39
3.8 Overview of Instructions ................................................................................................................... 40
3.8.1 Branch Command with Delay Slot ............................................................................................... 42
3.8.2 Branch Command without Delay Slot .......................................................................................... 44
3.9 EIT (Exception, Interruption, and Trap) ............................................................................................ 45
3.9.1 Interrupt Level of EIT ................................................................................................................... 46
3.9.2 Interrupt Stack Operation ............................................................................................................ 47
3.9.3 EIT Vector Table .......................................................................................................................... 48
3.9.4 Multiple EIT Processing ............................................................................................................... 49
3.9.5 Operation of EIT .......................................................................................................................... 51
3.10 Reset Sequence ............................................................................................................................... 55
3.11 Memory Access Mode ...................................................................................................................... 56
3.12 Clock Generation Section (Low Power Consumption Mechanism) .................................................. 59
3.12.1 Reset Factor Register (RSRR) and Watchdog Timer Cycle Control Register (WTCR) ............... 61
3.12.2 Standby Control Register (STCR) ............................................................................................... 63
3.12.3 Timebase Timer Clear Register (CTBR) ..................................................................................... 64
3.12.4 Gear Control Register (GCR) ...................................................................................................... 65
3.12.5 Watchdog Reset Generation Delay Register (WPR) ................................................................... 67
3.12.6 Reset Factor Retention ................................................................................................................ 68
3.12.7 Stop Status .................................................................................................................................. 70
3.12.8 Sleep Status ................................................................................................................................ 73
3.12.9 State Transition in Standby Mode ............................................................................................... 76
3.12.10 Gear Function .............................................................................................................................. 77
3.12.11 Clock Series Diagram .................................................................................................................. 80