Filter
Top Products
145
■ Capstan Input Control Register (CAPDVC)
Figure 6.2-4 Capstan Input Control Register (CAPDVC)
[bit7 to 0]:DIV7 to 0
Executes division control of the capstan input and edge detection control depending on the set value.
■ Capstan Mask Timer Control Register (CAPMTC)
Figure 6.2-5 Capstan mask timer control register (CAPMTC)
[bit7 to 0]:D7 to 0
Executes masking period control for the capstan input depending on the set value. When ΦMT is
specified as the clock cycle time selected by the mask timer clock select (CS) bit of the capstan control
register, and N is specified as the set value, the capstan input masking period TM is as follow.
TM= ΦMT × N ± ΦMT/2
However, N is set to 0, the mask processing does not perform.
7 6 5 4 3 2 1 0
XXXX XXXX
B
Initial value
bit
DIV7 DIV6 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0
R/W R/W R/W R/W R/W R/W R/W R/W
Access
Address: 000050
H
Set value Division control Edge detection
00
H
None Both edge detection
01
H
1-frequency division
Rising edge detection
02
H
2-frequency division
03
H
3-frequency division to
to to
FD
H
253-frequency division
FE
H
254-frequency division
FF
H
255-frequency division
7 6 5 4 3 2 1 0
XXXX XXXX
B
Initial value
bit
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
Access
Address: 000051
H