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328
Clock Mode Setting Register (SxMR)...................253
Clock Series Diagram............................................. 80
Command Operation............................................288
Comparison of External Access between Big Endian
and Little Endian .......................................... 97
Comparison Operation Instruction........................ 315
Configuration of Timer..........................................186
Connection Example with External Device... 103, 106
Construction of Internal Architecture...................... 26
Control in 16-bit Mode..........................................202
Controlling Method of FIFO..................................165
Coprocessor Absent Trap ...................................... 54
Coprocessor Control Instruction........................... 326
Coprocessor Error Trap.......................................... 54
Count Data Register (TxCD1, TxCD0) .................200
Crystal Oscillation Circuit ....................................... 22
D
Data Access ...........................................................38
Data Bus Width .............................................. 99, 105
Data Format ................................................... 99, 104
Data Register (GPRD)..........................................264
Dedicated Registers List ........................................29
Delay Divergence Instruction ...............................320
Delay Slot...............................................................54
Delayed Interrupt Control Register (DICR)...........227
Detection Result Register (BSRR) .......................270
Differences between Little Endian and Big Endian
...................................................................104
Direct Addressing Area ..........................................24
Direct Addressing Instruction ...............................326
Division Operation and PO Output.......................265
DLYI Bit of DICR .................................................. 228
Drum Control Register (DRMC) ...........................149
Drum Input ...........................................................142
Drum Input Control Register (DRMDVC) ............. 150
Drum Mask Timer Control Register (DRMMTC) ..151
E
EIT (Exception, Interruption, and Trap).................. 45
EIT Factor ..............................................................45
EIT Vector Table .................................................... 48
External Bus Access ............................................100
External Clock Mode (Only Timer 4) .................... 194
External Interrupt Enable Register (EIE)..............222
External Interrupt Request Flag (EIF) .................. 222
External Reset Input............................................... 22
F
Feature of 10-bit A/D Converter........................... 238
Feature of 10-bit General-purpose Prescaler ...... 262
Feature of 12-bit PWM......................................... 204
Feature of 8-/16-bit Timer/Counter ...................... 195
Feature of 8-bit Pulse Width Counter................... 212
Feature of Bit Search Module .............................. 268
Feature of CPU Architecture.................................. 26
Feature of External Bus Interface .......................... 86
Feature of External Interrupt ................................ 218
Feature of External Interrupt (INT0 to 2).............. 221
Feature of FRC Capture ...................................... 158
Feature of MB91191/MB91192 Series..................... 2
Feature of Programmable Pulse Generator (PPG0, 1)
................................................................... 168
Feature of Real Timing Generator (RTG) ............ 178
Feature of Serial I/O............................................. 250
Feature of Timer .................................................. 186
Flash Memory Status Register (FSTR)................ 284
FRC Count Data Register (FRCD2 to 0).............. 164
FR-CPU Programming Mode (16-bit, Read/Write)
................................................................... 286
FR-CPU ROM Mode (32-bit, Read Only)............. 286
Functions of I/O Port 0......................................... 119
Functions of I/O Port 1......................................... 121
Functions of I/O Port 2, 3..................................... 123
Functions of Port 4, 8, 9....................................... 131
Functions of Port 5............................................... 125
Functions of Port A, B.......................................... 135
Functions of Port C, D.......................................... 137
G
Gear Control Register (GCR)................................. 65
General-purpose Register...................................... 36
H
Half-word Access................................................. 109
Handling NC Pin .................................................... 22
Hard Conversion FIFO Data Register (HCFD) .... 243
Hard Conversion Status Register (HCSR)........... 242
Hardware Sequence Flag .................................... 292
How to Read the Instruction List.......................... 310
I
I/O Circuit Type ...................................................... 15
I/O Map ................................................................ 298
Initialization by Reset............................................. 55