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16.3 Operation of 10-bit A/D Converter
In terms of 10-bit A/D converter operations, A/D operation is possible using both
software and hardware conversions.
■ A/D Operation by Soft Conversion
In order to carry out A/D conversion using software conversion, first select the required channel from the
16 analog input pins AN0 to ANF. Enabled by writing "1" to the bit supported by the SCIS register.
●
For one channel
When only one channel is selected as the analog input pin for software conversion: Writing "1" to the
SSTR bit of the ADCH register starts the software conversion, and the SCS bit of the ADCH register will
be set to "1".
Writing "1" to the SSTR bit again during conversion initializes the conversion operation, and conversion
restarts.
When A/D conversion ends, the SCS bit of the ADCH register is reset to "0", and the SCEF bit of the
SCSR register is set to "1". Reading these status bits enables the end of the conversion to be determined. If
the interrupt for conversion completion needs to be generated, the SCIS bit of the SCSR register shall be set
to "1".
●
For multiple channel
When a number of channels are selected as the analog input pin for software conversion, automatically
checks whether or not each channel is selectable, then switches channels sequentially, starts up A/D
conversion, and stores the conversion results on a FIFO basis.
For the channel to be converted, writing "1" to the bit supported by the SCIS register and writing "1" to the
SSTR bit of the ADCH register starts software conversion, and the SCS bit of the ADCH register will be
set to "1". The conversion channel is selected from 0 to 15 sequentially, any channels that are not selected
by the SCIS register are not converted, and the next selected channel will be converted.
Writing "1" to the SSTR bit during conversion initializes the conversion operation, and conversion restarts
from channel 0.
When A/D conversion of all selected channels ends, the SCS bit of the ADCH register is reset to "0", and
the SCEF bit of the SCSR register is set to "1". If an interrupt for conversion completion needs to be
generated, the SCIS bit of the SCSR register shall be set to "1".
The A/D converted results can be stored FIFO up to six times, and they are automatically input on FIFO
basis at the end of A/D conversion. FIFO data can be retrieved by reading the SCFD register, then after
reading is automatically incremented in FIFO format, and the next data is output.
However, when the SCFD register is read through byte access, it is not incremented in FIFO format. When
the next conversion is carried out while FIFO basis is full (SCSR:SFUL_bit=1), the conversion results will
be overwritten at the sixth FIFO column.