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INDEX
Numerics
0 Detection........................................................... 271
0 Detection Data Register (BSD0) ....................... 269
1 Detection........................................................... 271
1 Detection Data Register (BSD1) ....................... 269
20-bit Delayed Divergence Macro Instruction ...... 323
20-bit Normal Divergence Macro Instruction........ 322
32-bit Delayed Divergence Macro Instruction ...... 325
32-bit Normal Divergence Macro Instruction........ 324
A
A/D Converter Control Register (ADCH, ADCL) .. 239
A/D Operation by Hard Conversion ..................... 246
A/D Operation by Soft Conversion....................... 245
Activating Watchdog Timer .................................... 82
Addition and Subtraction Instruction .................... 315
Address Offset Register (SxAO) .......................... 255
Area Mode Register 1 (AMD1)............................... 94
Area of Bus Interface ............................................. 88
Area Selection Register (ASR) and Area Mask
Register (AMR) ............................................ 91
At Power On........................................................... 22
Auto Algorithm Execute State .............................. 287
B
Bit Manipulation Instructions ................................ 316
Bit Ordering............................................................ 37
Block Diagram of 10-bit A/D Converter................ 238
Block Diagram of 10-bit General-purpose Prescaler
................................................................... 262
Block Diagram of 12-bit PWM.............................. 204
Block Diagram of 16-bit Timer (Timer 0 to 4)....... 188
Block Diagram of 8-/16-bit Timer/Counter ........... 195
Block Diagram of 8-bit Pulse Width Counter........ 212
Block Diagram of All MB91191/MB91192 Series..... 4
Block Diagram of Bit Search Module ................... 268
Block Diagram of Capstan Input .......................... 143
Block Diagram of Clock Generation Section.......... 60
Block Diagram of Delayed Interrupt Module ........ 226
Block Diagram of Drum Input............................... 148
Block Diagram of External Bus Interface ............... 87
Block Diagram of External Interrupt (INT0 to 2)... 221
Block Diagram of External Interrupt 1 (Key Input
Circuit) ....................................................... 219
Block Diagram of Flash Memory ..........................281
Block Diagram of FRC Capture ............................159
Block Diagram of Gear Control Section..................77
Block Diagram of Interrupt Controller ...................230
Block Diagram of Port 0........................................119
Block Diagram of Port 1........................................121
Block Diagram of Port 2, 3....................................123
Block Diagram of Port 4, 8, 9................................131
Block Diagram of Port 5........................................125
Block Diagram of Port 6, 7....................................128
Block Diagram of Port A, B...................................135
Block Diagram of Port C, D ..................................137
Block Diagram of Programmable Pulse Generator
(PPG0, 1) ...................................................168
Block Diagram of Real Timing Generator (RTG)..178
Block Diagram of Reel Input.................................152
Block Diagram of Reset Factor Retention Circuit ...68
Block Diagram of Serial I/O ..................................250
Block Diagram of Sleep Control Section ................73
Block Diagram of Stop Control Section ..................70
Block Diagram of Watchdog Control Section .........82
Branch Command with Delay Slot..........................42
Branch Command without Delay Slot.....................44
Bus Access of Big Endian ......................................97
Bus Access of Little Endian ....................................97
Bus Interface ..........................................................89
Byte Access..........................................................110
Byte Ordering .........................................................37
C
Cancellation of Interrupt Cause ............................235
CAPF Bit...............................................................215
Capstan Control Register (CAPC)........................144
Capstan Input .......................................................142
Capstan Input Control Register (CAPDVC)..........145
Capstan Mask Timer Control Register (CAPMTC)
...................................................................145
Capture Control Register (CAPC) ........................163
Capture Data ........................................................165
Capture Data Registers (CAPD2 to 0)..................164
Capture Input Control Register (CIC1, CIC0) .......160
Capture Source Register (CAPS).........................164
Change Point Detection........................................272
Change Point Detection Data Register (BSDC) ...269