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CHAPTER 3 CPU
■ Block Diagram of Clock Generation Section
Figure 3.12-2 Block Diagram of Clock Generation Section
State
transition
control
circuit
RSRR register
WPR register
CTBR register
Watchdog F/F
Timebase timer
STCR regiter
GCR register
CPU gear
Peripheral
gear
1/ 2
PLL
Reset
generation
F/F
Osci-
llation
circuit
Internal
clock
generation
circuit
M
P
X
[Stop/Sleep control unit]
CPU clock
Internal bus clock
Internal peripheral clock
Internal interrupt
Internal reset
STOP state
SLEEP state
CPU hold request
Internal reset
[Reset factor circuit]
[Watchdog control unit]
Count
clok
Power-on detection
RST pin
X0
X1
[Gear control unit]
R-bus