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253
The read value of this bit is always "1".
[bit2]:CSE
It is the chip select auto-transfer enable bit.
[bit1]:DIR
It is transfer direction control bit.
[bit0]:ST
It is serial transfer start bit.
This bit will be cleared to "0" when serial data transfer ends.
■ Clock Mode Setting Register (SxMR)
Figure 17.2-2 Clock mode setting register (SxMR)
[bit7, 6]:
There are unused bits.
[bit5]:
It is undefined bit. (Reserved)
[bit4]:IC1
0 Automatic transfer is disabled.
1 Automatic transfer is enabled.
0
Transfer reception data to RAM per transmitting RAM data
(transmission/reception mode)
1 Transmit RAM data (Transmission mode)
0 Transfer Stop
1 Transfer start
7 6 5 4 3 2 1 0
--0X XXXX
B
Initial value
bit
IC1 IC0 SC2 SC1 SC0
R/W R/W R/W R/WR/W R/W
Access