Filter
Top Products
147
Figure 6.2-8 Operation timing diagram of Mask Timer
●
Limitation on using
When double mode is specified for the capstan input, do not set "00
H
" to the capstan input control register.
It may cause the malfunction.
CFG
frequency division
Output edge
Mask period
DVCFG output
CFGD bit
M.T Load
CAPMTC
Wclr Wclr