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329
Initiation Procedure of Real Timing Generator (RTG)
................................................................... 183
Instruction Format ................................................ 313
Instruction List of FR Series................................. 314
Internal Memory Area .......................................... 276
Interrupt Control ................................................... 287
Interrupt Control Register (ICRxx) ....................... 232
Interrupt Function................................................. 259
Interrupt level of EIT............................................... 46
Interrupt Number.................................................. 228
Interrupt Stack........................................................ 47
Interrupt Vector .................................................... 306
K
Key Input Control Register (KEYC)...................... 220
Key Input Status Register (KEYS) ....................... 220
L
Level Mask to Interruption/NMI .............................. 46
Limitations for Branch Command with Delay ......... 43
Little Endian Register (LER) .................................. 96
Logical Operation Instruction ............................... 315
M
Measurement Accuracy of Peripheral Circuit Relative
to FRC and Output Timing Accuracy ......... 308
Memory Loading Instruction................................. 318
Memory Map .................................................... 24, 39
Memory Map and Sector Construction ................ 282
Memory Store Instruction..................................... 318
Mode (MD0 to MD2) Pin ........................................ 22
Mode Data ............................................................. 57
Mode Pin................................................................ 56
Mode Register (MODR) ......................................... 57
Multiplication and Division Instructions ................ 316
Multiplication and Division Result Register (MDH/
MDL) ............................................................ 31
N
Normal Divergence (There is no delay) Instruction
................................................................... 319
Note on Using External Clock ................................ 22
Notes on Writing to Mode Register (MODR).......... 58
O
Operation ............................................................. 151
Operation in 8-bit Internal Clock Mode ................ 201
Operation Mode ..................................................... 56
Operation Mode of Serial I/O ............................... 258
Operation of 12-bit PWM ......................................208
Operation of 16-bit Timer (Timer 0 to 4) ...............193
Operation of 8-bit External Clock Mode (Event
Counter) .....................................................201
Operation of Branch Command with Delay Slot .....42
Operation of Branch Command without Delay Slot 44
Operation of Capstan Input ..................................146
Operation of Drum Input .......................................151
Operation of EIT .....................................................51
Operation of External Interrupt (INT0 to 2) ...........223
Operation of External Interrupt 1 (Key Input Circuit)
...................................................................220
Operation of INT Instruction ...................................52
Operation of Reel Input ........................................155
Operation of RETI Instruction .................................54
Operation of Serial I/O..........................................257
Operation of Step Trace Trap.................................53
Operation of Undefined Instruction Exception ........53
Output Data Register (RTGxD) ............................182
Output Operation of PPG .....................................175
Overview of Flash Memory...................................280
Overview of Instructions .........................................40
Overview of Sleep Status .......................................73
Overview of Stop Status .........................................70
P
Package Dimension (FLGA-144)..............................6
Package Dimension (LQFP-120)..............................5
Pin ............................................................................9
Pin Assignment (FLGA-144).....................................8
Pin Assignment (LQFP-120).....................................7
Pin Function List .......................................................9
Port 6, 7 ................................................................127
Power Supply Pin ...................................................22
PPG0 Frame Data ................................................174
PPG1 Frame Data ................................................174
PPGx Control Register (PPGxC)..........................171
Precaution when Clear IF Flag .............................176
Precautions.............................................................21
Precautions when Designing ..................................18
Precautions when Mounting Package ....................19
Prescaler Control Register (GPRC)......................263
Priority Level of EIT Factor Acceptance .................49
Priority Order Evaluation ......................................233
Priority Order of A/D Conversion ..........................246
Program Access .....................................................38
Program Counter (PC)............................................29
Program Example of External Bus Operation.......113