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CHAPTER 16 10-bit A/D Converter
●
ADCL
Figure 16.2-2 A/D converter control register (ADCL)
[bit7 to 6]:Test
Please set "0".
[bit5]:Test
It is test bit.
[bit4, 3]:
There are unused bit.
[bit2 to 0]:Hi2 to 0
There are analog input selection bits for hard conversion.
■ Soft Conversion Analog Input Selection Register (SCIS)
Figure 16.2-3 Soft conversion analog input selection register (SCIS)
[bit15 to 0]:iF to 0
There are analog input selection bits for soft conversion.
When a number of inputs are selected, all selected inputs are converted sequentially.
7 6 5 4 3 2 1 0
000- -XXX
B
Initial value
bit
Test Test Test
Hi2 Hi1 Hi0
R/W R
R/W R/W R/WR/W
Address: 0000A1
H
Access
Hi2 Hi1 Hi0 Selection analog input
0 0 0 AN-0
0 0 1 AN-1
0 1 0 AN-2
0 1 1 AN-3
1 0 0 AN-4
1 0 1 AN-5
1 1 0 AN-6
1 1 1 AN-7
0000 0000
H
Initial value
bit
R/W
iF iE iD iC iB iA i9 i8 i7 i6 i5 i4 i3 i2 i1 i0
1514131211109876543210
Address: 0000A2
H
Access
0 Input non-selection
1 Input selection