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CHAPTER 3 CPU
3.9.1 Interrupt Level of EIT
Interrupt levels is controlled by 0 to 31 by five bits.
■ Interrupt level of EIT
The allocation of each level is as follow.
It is a level of 16 to 31 that the operation is possible.
Undefined command exception, coprocessor absence trap, coprocessor error trap and INT instruction are
unaffected by the interrupt level. Moreover, ILM is occasionally changed.
■ Level Mask to Interruption/NMI
When NMI and interrupt requests are generated, the interrupt level held by the interrupt factor is compared
with the level mask value held by the ILM. And, when the following condition consists, the mask is done,
and the demand is not accepted.
Interrupt level held by factor ≥ Level mask value
Table 3.9-1 Interrupt level
Interrupt level
Factor Remark
2 decimal
number
10 decimal
number
00000 0
(System reservation)
When the original value of the ILM is 16 to 31,
values within this range cannot be set as the ILM
by the program.
00001 1
00010 2
00011 3
00100 4 INTE instruction, step trace trap
00101 to
01110
5 to 14 (System reservation)
01111 15 NMI (for user)
10000 to
11110
16 to 30 Interrupt
When ILM is set, it is a user interruption
interdiction.
11111 31 - When ICR is set, it is an interruption interdiction.