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CHAPTER 15 Interrupt Controller
15.2 Interrupt Control Register (ICRxx)
This is interrupt control register. One is set per interrupt input, and sets the interrupt
level for the interrupt request to be supported.
■ Interrupt Control Register (ICRxx)
Figure 15.2-1 Interrupt control register (ICRxx)
[bit4 to 0] ICR4 to 0
The interrupt level of the interrupt request to be supported is specified by the interrupt level setting bit.
When the interrupt level set to this register is the level mask value that has been set to the ILM register
of the CPU or higher, the interrupt request is masked by the CPU side.
Initialized to 11111
B
by reset.
Table 15.2-1 is shown the interrupt-level setting bits that can be set and the corresponding interrupt
levels.
*: ICR4 is fixed "1" and cannot be "0".
7 6 5 4 3 2 1 0
---1 1111
B
Initial value
bit
ICR4 ICR3 ICR2 ICR1 ICR0
R R/W R/W R/W R/W
Access
Table 15.2-1 Level setting and corresponding interrupt levels
ICR4 ICR3 ICR2 ICR1 ICR0 Interrupt level
0 0 0 0 0 0
0 1 1 1 0 14
0 1 1 1 1 15
1 0 0 0 0 16 Highest level that can be set
1 0 0 0 1 17
1 0 0 1 0 18
1 0 0 1 1 19
1 0 1 0 0 20
1 0 1 0 1 21
1 0 1 1 0 22
1 0 1 1 1 23
1 1 0 0 0 24
1 1 0 0 1 25
1 1 0 1 0 26
1 1 0 1 1 27
1 1 1 0 0 28
1 1 1 0 1 29
1 1 1 1 0 30
1 1 1 1 1 31 Disables the interrupt.
System reservation
(low)
(High)