Filter
Top Products
149
■ Drum Control Register (DRMC)
Figure 6.3-3 Drum Control Register (DRMC)
[bit7]:DFGD
This is the division FG edge detection flag during drum masking.
[bit6]:DFCLR
This is the edge detection flag clear bit during drum masking.
The read value of this bit is always "1".
[bit5]:DMTS
This is the drum mask timer status flag.
[bit4]:MTCS
This is clock source selection bit of mask timer.
[bit3]:DINV
This is the polarity control bit of the DFG input signal.
7 6 5 4 3 2 1 0
X1X0 0X10
B
Initial value
bit
DFCG DFCLR DMTS MTCS DINV DPGD DPCLR DPGE
R W R R/W R/W R W R/W
Access
Address: 000053
H
0 Without edge detection
1 With edge detection
0 Clear the DFGD flag.
1 None
0 Mask released
1 Masking
Selection Clock in fch:@20MHz
0
2
10
/fch (FRC9)
51.2 µs
1
2
14
/fch (FRC13)
819.2 µs
0 Input through
1 Input inversion