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CHAPTER 3 CPU
3.3.1 Program Status Register (PS)
The register retains the program status, and is separated into three parts, ILM, SCR, and
CCR.
A bit undefined in figure is reservation all bit. When the register is read, "0" is always
read. Writing is invalid.
■ Program Status Register (PS)
Figure 3.3-8 shows the configuration of the program status register (PS).
Figure 3.3-8 Program status register (PS)
●
Condition code register (CCR)
Figure 3.3-9 shows the configuration of the condition code register (CCR).
Figure 3.3-9 Condition code register (CCR)
The function of each bit is explained as follow.
[bit5] S: Stack flag
This bit specifies the stack pointer to be used as R15.
This bit is cleared to "0" by a reset.
Select the SSP when the RETI instruction is executed.
31 20 16 10 8 7 0
ILM
SCR
CCR
bit
7 6 5 4 3 2 1 0 Initial value
S I N Z V C --00XXXX
H
bit
Value Function
0
The system stack pointer (SSP) is used as R15. When the EIT occurs, this bit is
automatically set to "0". (Note that a value saved on the stack is the value before it is
cleared)
1 The user stack pointer (USP) is used as R15.