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3.12.1 Reset Factor Register (RSRR) and Watchdog Timer Cycle
Control Register (WTCR)
The reset factor register (RSRR) retains reset types generated, and the watchdog timer
cycle control register (WTCR) specifies the cycle for the watchdog timer.
■ Reset Factor Register (RSRR) and Watchdog Timer Cycle Control Register (WTCR)
Figure 3.12-3 Reset factor register (RSRR) and watchdog timer cycle control register (WTCR)
[bit7]: PONR
When this bit is "1", it indicates that the previously generated reset was a power-on reset. When this bit
is "1", contents other than this bit of this register are invalid.
[bit6]: (Reserved)
It is reserved bit. The reading value is undefined.
[bit5]: WDOG
When this bit is "1", it indicates that the previously generated reset was a watchdog reset.
[bit4]: ERST
When this bit is "1", it indicates that the previously generated reset was caused by the external reset pin.
[bit3]: SRST
When this bit is "1", it indicates that the previously generated reset was caused by the software reset
request.
[bit2]: (Reserved)
It is reserved bit. The reading value is undefined.
[bit1, 0]: WT1, 0
These bits specify the cycle of the watchdog timer. The bits and the selected cycle have the following
relationship. These bits are initialized when the entire reset is generated.
Initial value after
Power ON
PONR WDOG ERST SRST WT1 WT0 1XXX XXXXB
76543210
Address: 000480
H
bit
R RRR WW
Access