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16.2 Register of 10-bit A/D Converter
The register configuration/functions of the 10-bit A/D converter is shown.
■ A/D Converter Control Register (ADCH, ADCL)
●
ADCH
Figure 16.2-1 A/D converter control register (ADCH)
[bit7 to 5]:Test
It is test bit.
[bit4]:ADMV
It is flag to indicate under A/D conversion.
[bit3]:HCNS
It is hard start hold flag.
[bit2]:HCS
It is hard conversion status flag.
[bit1]:SCS
It is soft conversion status flag.
[bit0]:SSTR
It is soft conversion start bit.
When this bit is read, "0" is always read.
7 6 5 4 3 2 1 0
XXX0 0000
B
Initial value
bit
RRRRRRRR
Test Test Test
ADMV HCNS HCS SCS SSTR
Address: 0000A0
H
Access
0 Not Under the conversion
1 Under the conversion
0 No conversion hold by hard start (without nest)
1 Conversion hold by hard start (with nest)
0 Conversion complete by hard start
1 Under the conversion by hard start
0 Conversion complete by soft start
1 Under the conversion by soft start
0 None
1 Start/restart soft conversion (writing under conversion)