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CHAPTER 3 CPU
3.2 CPU Architecture
The FR20 CPU is a high performance core that adopts highly functional commands for
the embedded application as well as RISC architecture.
■ Feature of CPU Architecture
●
Adoption of RISC architecture
• Basic instruction: one instruction one cycle
●
32 bit architecture
• General-purpose register 32 bits × 16
●
Linear memory space of 4 GB
●
Installing of multipliers
• 32 bits x multiplication 32 bits: 5 cycles
• 16 bits x multiplication 16 bits: 3 cycles
●
Reinforcement of interruption processing function
• High-speed response speed (6 cycles)
• Support for multiple interrupts
• Level mask function (16 levels)
●
Reinforcement of instruction for I/O operation
• Memory memory transfer operation
• Bit processing instruction
●
High code efficiency
• 16 bits in basic instruction word length
●
Low power consumption
• Sleep mode, stop mode
■ Construction of Internal Architecture
The FR20 CPU adopts the Harvard architecture structure whereby the command bus and data bus are
independent.
The on chip command cache is connected to the command bus (T-bus). A 32-bit <--> 16-bit bus converter
is connected to the data bus (D-bus), and performed interfaces between the CPU and peripheral resources.
A Harvard <--> Princeton bus converter is connected to both the I-bus and D-bus, performed and interfaces
between the CPU and bus controller.