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20-bit Delayed Divergence Macro Instruction
Table E-17 20-bit Delayed divergence macro instruction
Mnemonic Operation Remark
*CALL20:D label20,Ri Address of the following instruction +2
→
RP,
label20→
PC
Ri: Temporary register (Refer to reference 1.)
*BRA20:D label20,Ri
*BEQ20:D label20,Ri
*BNE20:D label20,Ri
*BC20:D label20,Ri
*BNC20:D label20,Ri
*BN20:D label20,Ri
*BP20:D label20,Ri
*BV20:D label20,Ri
*BNV20:D label20,Ri
*BLT20:D label20,Ri
*BGE20:D label20,Ri
*BLE20:D label20,Ri
*BGT20:D label20,Ri
*BLS20:D label20,Ri
*BHI20:D label20,Ri
label20
→
PC
if(Z==1)thenlabel20→
PC
↑
s/Z==0
↑
s/C==1
↑
s/C==0
↑
s/N==1
↑
s/N==0
↑
s/V==1
↑
s/V==0
↑
s/VxorN==1
↑
s/VxorN==0
↑
s/(VxorN)orZ==1
↑
s/(VxorN)orZ==0
↑
s/CorZ==1
↑
s/CorZ==0
Ri: Temporary register (Refer to reference 2.)
Ri: Temporary register (Refer to reference 3.)
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
Reference1: CALL20:D
1) When label20-PC-2 is - 0x100 - + 0xfe, the instruction is generated as follows.
CALL:D label12
2) When label20-PC-2 is outside the area as per 1) and includes an external reference symbol, the command is generated as
follows.
LDI:20 #label20,Ri
CALL:D @Ri
Reference 2: BRA20:D
1) When label20-PC-2 is - 0x100 - + 0xfe, the instruction is generated as follows. x
BRA:D label9
2) When label20-PC-2 is outside the area as per 1) and includes an external reference symbol, the command is generated as
follows.
LDI:20 #label20,Ri
JMP:D @Ri
Reference 3: Bcc20:D
1) When label20-PC-2 is - 0x100 - + 0xfe, the instruction is generated as follows.
Bcc:D label9
2) When label20-PC-2 is outside the area as per 1) and includes an external reference symbol, the command is generated as
follows.
Bxcc false xcc is a contradiction condition of cc.
LDI:20 #label20,Ri
JMP:D @Ri
false: