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■ Soft Conversion Status Register (SCSR)
Figure 16.2-4 Soft conversion status register (SCSR)
[bit7]:SCEF
It is soft conversion end flag.
[bit6]:SECR
It is SCEF clear bit.
The read value of this bit is always "1".
[bit5]:SCIE
It is soft conversion interrupt enable bit.
The interrupt request is generated when SCEF=1 is SCIE=1.
[bit4, 3]:
It is an unused bit.
[bit2]:SFCR
It is soft conversion FIFO clear bit.
The read value of this bit is always "0".
[bit1]:SFUL
It is soft conversion FIFO full bit.
[bit0]:SEMP
It is soft conversion FIFO empty bit.
7 6 5 4 3 2 1 0
X10- -001
B
Initial value
bit
SCEF SECR SCIE
SFCR SFUL SEMP
R
R/W R RWW
Address: 0000A5
H
Access
0 None or Under the conversion
1 Conversion complete
0 Clear soft conversion end flag.
1 None
0 Interrupt interdiction
1 Interruption permission
0 None
1 Clear FIFO.
0 Status that data can input to FIFO
1 FIFO full
0 Status that data is retained in FIFO
1 FIFO empty