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CHAPTER 17 Serial I/O
17.2 Register of Serial I/O
The register configuration/functions of the serial I/O is shown.
■ Serial Control Register (SxCR)
Figure 17.2-1 Serial control register (SxCR)
[bit7]:SIF
It is serial I/O transfer completion flag.
[bit6]:ICLR
It is transfer completion flag clear bit.
The read value of this bit is always "1".
[bit5]:SIE
It is interrupt enable bit.
[bit4]:CSAF
It is forced end flag at chip select transfer.
[bit3]:ACLR
It is forced end flag clear bit.
7 6 5 4 3 2 1 0
0100 1000
B
Initial value
bit
SIF ICLR SIE CSAF ACLR CSE DIR ST
RRWWR/W R/W R/W R/W
Access
0 Serial data transfer does not complete.
1 Serial data transfer completes.
0 Clear transfer completion flag
1 None
0 Interruption is disabled.
1 Interruption is enabled.
0 Automatic transfer normally ends by chip select.
1 Forcibly ends by chip select under transfer.
0 Clear transfer completion flag.
1 None