Filter
Top Products
S3F80JB RESET
8-7
V
LVD
V
DD
0.4V
DD
a. System reset is not occurred.
b. System reset is occurred by internal POR circuit.
If "Vreset > VIH", the operating status is in STOP mode and IPOR / LVD control bit of smart
option is '0', LVD circuit is disabled in the S3F80JB.
Va
b
NOTE:
Va is a schmitt trigger input signal of internal power-on reset (IPOR).
0.85V
DD
Reset Pulse Width
a
b
Figure 8-6. Reset Timing Diagram for The S3F80JB in STOP mode by IPOR
EXTERNAL INTERRUPT RESET
When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’and chip is in stop mode, if external interrupt
is occurred by among the enabled external interrupt sources, from INT0 to INT9, reset signal is generated.