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COMPARATOR S3F80JB
14-4
LSBMSB
Comparator Mode Register (CMOD)
E9H, Set1, Bank 1, R/W
Reference Voltage Selection Bits
Selected Vref=Vdd x (N + 0.5)/16, n=0 to 15
Comparator Enale/Disable Bit
0:Comparator operation disable
1:Comparator operation enable
Not used for S3F80JB.
External /Internal Reference Selection Bit
0: Internal reference, CIN0-3:analog input
1: External reference,CIN0-2: analog input, CIN3:reference input
Conversion Timer Control Bit
0: 8x2
7
/fosc,256us at 8MHz
1: 8x2
4
/fosc,32us at 8MHz
.7 .6 .5 .4 .3 .2 .1 .0
Figure 14-3. Comparator Mode Register (CMOD)
.7 .6 .5 .4 .3 .2 .1 .0 LSBMSB
Comparator Input Selection Register (CMPSEL)
EBH, Set1, Bank 1, R/W
P2.7 Function Selection Bit
0:Normal I/O selection
1:Alternative function enable: CIN3
Not used for S3F80JB.
P2.6 Function Selection Bit
0:Normal I/O selection
1:Alternative function enable: CIN2
P2.4 Function Selection Bit
0:Normal I/O selection
1:Alternative function enable: CIN0
P2.5 Function Selection Bit
0:Normal I/O selection
1:Alternative function enable: CIN1
Figure 14-4. Comparator Input Selection Register (CMPSEL)