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CONTROL REGISTERS S3F80JB
4-14
IMR — Interrupt Mask Register DDH Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
x x x x x x x x
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode
Register addressing mode only
.7 Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.7–P0.4
0 Disable (mask)
1 Enable (un-mask)
.6 Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.3–P0.0
0 Disable (mask)
1 Enable (un-mask)
.5 Interrupt Level 5 (IRQ5) Enable Bit; External Interrupts P2.7–P2.4
0 Disable (mask)
1 Enable (un-mask)
.4 Interrupt Level 4 (IRQ4) Enable Bit; External Interrupts P2.3–P2.0
0 Disable (mask)
1 Enable (un-mask)
.3
Interrupt Level 3 (IRQ3) Enable Bit; Timer 2 Match or Overflow
0 Disable (mask)
1 Enable (un-mask)
.2 Interrupt Level 2 (IRQ2) Enable Bit; Counter A Interrupt
0 Disable (mask)
1 Enable (un-mask)
.1 Interrupt Level 1 (IRQ1) Enable Bit; Timer 1 Match or Overflow
0 Disable (mask)
1 Enable (un-mask)
.0 Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match or Overflow
0 Disable (mask)
1 Enable (un-mask)