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EMBEDDED FLASH MEMORY INTERFACE S3F80JB
15-6
FLASH MEMORY CONTROL REGISTERS (USER PROGRAM MODE)
FLASH MEMORY CONTROL REGISTER (FMCON)
FMCON register is available only in user program mode to select the flash memory operation mode; sector erase,
byte programming, and to make the flash memory into a hard lock protection.
Flash Memory Control Register (FMCON)
EFH , Set1 , Bank1 , R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Flash (Erase or Hard Lock Protection)
Operation Start Bit
0 = Operation stop
1 = Operation start
(This bit will be cleared automatically just
after erase operation.)
Flash Memory Mode Selection Bits
0101: Programming mode
1010: Erase mode
0110: Hard lock mode
others: Not used for S3F80JB
Not used for S3F80JB.
Figure 15-3. Flash Memory Control Register (FMCON)
The bit 0 of FMCON register (FMCON.0) is a bit for the operation start of Erase and Hard Lock Protection.
Therefore, operation of Erase and Hard Lock Protection is activated when you set FMCON.0 to “1”. If you write
FMCON.0 to 1 for erasing, CPU is stopped automatically for erasing time (min.10ms). After erasing time, CPU is
restarted automatically. When you read or program a byte data from or into flash memory, this bit is not needed to
manipulate.
FLASH MEMORY USER PROGRAMMING ENABLE REGISTER (FMUSR)
The FMUSR register is used for a safe operation of the flash memory. This register will protect undesired erase or
program operation from malfunctioning of CPU caused by an electrical noise. After reset, the user-programming
mode is disabled, because the value of FMUSR is “00000000B” by reset operation. If necessary to operate the
flash memory, you can use the user programming mode by setting the value of FMUSR to “10100101B”. The
other value of “10100101B”, user program mode is disabled.
Flash Memory User Programming Enable Register (FMUSR)
EEH, Set1, Bank 1, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Flash Memory User Programming Enable Bits
10100101: Enable user programming mode
Other values: Disable user programming mode
Figure 15-4. Flash Memory User Programming Enable Register (FMUSR)