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S3F80JB RESET
8-1
8 RESET
OVERVIEW
Resetting the MCU is the function to start processing by generating reset signal using several reset schemes.
During reset, most control and status are forced to initial values and the program counter is loaded from the reset
vector. In case of S3F80JB, reset vector can be changed by smart option. (Refer to the page 2-3 or 15-5).
RESET SOURCES
The S3F80JB has six-different system reset sources as following
– The External Reset Pin (nRESET): When the nRESET pin transiting from VIL (low input level of reset
pin) to VIH (high input level of reset pin), the reset pulse is generated on the condition of “VDD ≥
VLVD“ in any operation mode.
– Watch Dog Timer (WTD): When watchdog timer enables in normal operating, a reset is generated
whenever the basic timer overflow occurs.
– Low Voltage Detect (LVD): When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘1’, and
VDD is changed in condition for LVD operation regardless of operation mode, reset occurs. Although
IPOR/LVD Control Bit (smart option bit [7] @03FH) is set to ‘0’, if the operation mode is not in STOP
mode, reset signal is generated by LVD.
– Internal Power-ON Reset (IPOR): When IPOR/LVD Control Bit (smart option bit[7] @ 03FH) is set to ‘0’,
and VDD is changed in condition for IPOR operation in STOP Mode, a reset is generated.
– External Interrupt (INT0-INT9): When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’
and chip is in stop mode, if external interrupt is enabled, external interrupts by P0 and P2 generate the
reset signal.
– STOP Error Detection & Recovery (SED&R): When IPOR/LVD Control Bit (smart option bit [7] @ 03FH)
is set to ‘0’ and chip is in stop or abnormal state, the falling edge input of P0 or P2.4-P2.7 generates the
reset signal regardless of external interrupt enable/disable.