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vi S3F80JB MICROCONTROLLER
Table of Contents (Continued)
Chapter 5 Interrupt Structure
Overview ....................................................................................................................................................5-1
Interrupt Types...................................................................................................................................5-2
Interrupt Vector Addresses.................................................................................................................5-5
Enable/Disable Interrupt Instructions (EI, DI) .....................................................................................5-7
System-Level Interrupt Control Registers...........................................................................................5-7
Interrupt Processing Control Points....................................................................................................5-8
Peripheral Interrupt Control Registers................................................................................................5-9
System Mode Register (SYM)............................................................................................................5-10
Interrupt Mask Register (IMR)............................................................................................................5-11
Interrupt Priority Register (IPR)..........................................................................................................5-12
Interrupt Request Register (IRQ) .......................................................................................................5-14
Interrupt Pending Function Types ......................................................................................................5-15
Interrupt Source Polling Sequence.....................................................................................................5-16
Interrupt Service Routines..................................................................................................................5-16
Generating interrupt Vector Addresses ..............................................................................................5-17
Nesting of Vectored Interrupts............................................................................................................5-17
Instruction Pointer (IP) .......................................................................................................................5-17
Fast Interrupt Processing...................................................................................................................5-17
Chapter 6 Instruction Set
Overview ....................................................................................................................................................6-1
Flags Register (FLAGS).....................................................................................................................6-6
Flag Descriptions ...............................................................................................................................6-7
Instruction Set Notation......................................................................................................................6-8
Condition Codes.................................................................................................................................6-12
Instruction Descriptions......................................................................................................................6-13
Chapter 7 Clock Circuit
Overview ....................................................................................................................................................7-1
System Clock Circuit..........................................................................................................................7-1
Clock Status During Power-Down Modes ..........................................................................................7-2
System Clock Control Register (CLKCON) ........................................................................................7-3