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S3F80JB BASIC TIMER and TIMER 0
10-3
BASIC TIMER FUNCTION DESCRIPTION
Watch-dog Timer Function
You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to
any value other than '1010B'. (The '1010B' value disables the watch-dog function.) A reset clears BTCON to '00H',
automatically enabling the watch-dog timer function. A reset also selects the CPU clock (as determined by the
current CLKCON register setting), divided by 4096, as the BT clock.
A reset is generated whenever the basic timer overflow occurs. During normal operation, the application program
must prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value
must be cleared (by writing a "1" to BTCON.1) at regular intervals.
If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation
will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal
operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken
by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically.
Oscillation Stabilization Interval Timer Function
You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when
Stop mode has been released by an external interrupt.
In Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts
increasing at the rate of fOSC/4096 (for reset), or at the rate of the preset clock source (for an external interrupt).
When BTCNT.3 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate
the clock signal off to the CPU so that it can resume normal operation.
In summary, the following events occur when Stop mode is released:
1. During Stop mode, a power-on reset or an external interrupt occurs to trigger the Stop mode release and
oscillation starts.
2. If a power-on reset occurred, the basic timer counter will increase at the rate of f
OSC
/4096. If an external
interrupt is used to release Stop mode, the BTCNT value increases at the rate of the preset clock source.
3. Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows.
4. When a BTCNT.3 overflow occurs, normal CPU operation resumes.