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RESET S3F80JB
8-10
BACK-UP MODE
For reducing current consumption, S3F80JB goes into Back-up mode. If external reset pin is low state or a falling
level of V
DD
is detected by LVD circuit on the point of V
LVD
, chip goes into the back-up mode. Because CPU and
peripheral operation were stopped due to oscillation stop, the supply current is reduced. In back-up mode, chip
cannot be released from stop state by any interrupt. The only way to release back-up mode is the system-reset
operation by interactive work of reset pin and LVD circuit. The system reset of watchdog timer is not occurred in
back up mode.
LVD
Rising Edge
Detector
nRESET
Back-Up Mode
Falling Edge
Detector
V
DD
<=V
LVD
Noise
Filter
V
re set
<=V
IL
Figure 8-7. Block Diagram for Back-up Mode
Normal OperationNormal Operation Back up Mode
Voltage [V]
V
LVD
V
DD
Low level
detect voltage
Falling edge detected,
oscillation stop.
(V
DD
< V
LVD
)
Rising edge detected
(V
DD
>= V
LVD
)
Reset Pulse generated,
oscillation starts
Slope of nRESET & V
DD
Pin
NOTES:
1, When the rising edge is detected by LVD circuit, Back-up mode is relesased. (V
LVD
=
V
DD
)
2. When the falling edge is detected by LVD circuit, Back-up mode is activated (V
LVD
> V
DD
)
Figure 8-8. Timing Diagram for Back-up Mode Input and Released by LVD