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RESET S3F80JB
8-8
STOP ERROR DETECTION & RECOVERY
When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’and chip is in stop or abnormal state, the
falling edge input of P0 and P2.4-P2.7 generates the reset signal.
Refer to following table and figure for more information.
Table 8-1. Reset Condition in STOP Mode When IPOR / LVD Control Bit is “1” (always LVD-On)
Condition
Slope of V
DD
V
DD
The voltage level of reset pin
(Vreset)
Reset
Source
System Reset
V
DD
≥ V
LVD
Vreset ≥ V
IH
LVD circuit System reset occurs
V
DD
≥ V
LVD
Vreset < V
IH
– No system reset
Rising up from
V
DD
< V
LVD
V
DD
< V
LVD
Transition from
“Vreset < V
IL
” to “V
IH
< Vreset”
– No system reset
Standstill
(V
DD
≥ V
LVD
)
V
DD
≥ V
LVD
Transition from
“Vreset < V
IL
” to “V
IH
< Vreset”
Reset pin System reset occurs
Table 8-2. Reset Condition in STOP Mode When IPOR / LVD Control Bit is “0”
Condition
Slope of V
DD
V
DD
The voltage level of reset pin
(Vreset)
Reset
Source
System Reset
V
DD
≥ V
LVD
Vreset ≥ V
IH
– No system reset
V
DD
> V
LVD
Vreset < V
IH
– No system reset
Rising up from
0.4 V
DD
< V
DD
<
V
LVD
V
DD
< V
LVD
Transition from
“Vreset < V
IL
” to “V
IH
< Vreset”
– No system reset
V
DD
≥ V
LVD
Vreset ≥ V
IH
Internal POR System reset occurs
V
DD
> V
LVD
Vreset < V
IH
– No system reset
Rising up from
V
DD
< 0.4V
DD
V
DD
< V
LVD
Transition from
“Vreset < V
IL
” to “V
IH
< Vreset”
– No system reset
Standstill
(V
DD
≥ V
LVD
)
V
DD
≥ V
LVD
Transition from
“Vreset < V
IL
” to “V
IH
< Vreset”
Reset pin System reset occurs
NOTE: IPOR / LVD control bit is included in smart option at address 003FH. (3FH.7)