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INTERRUPT STRUCTURE S3F80JB
5-10
SYSTEM MODE REGISTER (SYM)
The system mode register, SYM (DEH, Set 1, Bank0), is used to globally enable and disable interrupt processing
and to control fast interrupt processing (See Figure 5-5).
A reset clears SYM.7, SYM.1, and SYM.0 to "0". The 3-bit value, SYM.4–SYM.2, is for fast interrupt level
selection and undetermined values after reset. SYM.6 and SYM5 are not used.
The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0
value of the SYM register. An Enable Interrupt (EI) instruction must be included in the initialization routine, which
follows a reset operation, in order to enable interrupt processing. Although you can manipulate SYM.0 directly to
enable and disable interrupts during normal operation, we recommend using the EI and DI instructions for this
purpose.
System Mode Register (SYM)
DEH, Set 1, Bank 0, R/W
.7 - - .4 .3 .2 .1 .0MSB LSB
Fast Interrupt Level
Selection Bits:
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Not used
Global Interrupt Enable
Bit:
0 = Disable all
1 = Enable all
Fast Interrupt Enable Bit:
0 = Disable fast
1 = Enable fast
External Interface Tri-state Enable Bit:
0 = Normal operation
(Tri-state disabled)
1 = High impedance
(Tri-state enabled)
NOTE:
In case of S3F80JB, an external memory interface is not implemented.
Figure 5-5. System Mode Register (SYM)