Intel 307017-001 TV Cables User Manual


 
Programmer’s Reference Manual 111
Intel® High Definition Audio BIOS Considerations
4. De-assert AC_RESET# bit to take the link out of RESET# (NABMBAR at D30:F2:Reg14h +
offset 2Ch[1]=1).
5. Wait ~20ms for AC'97 codec driven BIT_CLK startup.
6. Write a 0 to the Intel® HD Audio/AC97# bit (D27:F0:Reg40h[0]=0) to ensure that AC’97
mode is selected.
7. Make sure that CLKDET# bit is cleared by writing a 1 and then a 0 to the CLKDETCLR bit.
8. Write a 1 to the CLKDETEN bit to enable the clock detection circuit.
9. Write a 0 to the CLKDETEN bit.
10. Read the CLKDET# bit.
11. If CLKDET# is clear(==0), then the codec(s) are AC'97. Disable and hide the Intel® HD
Audio function. Skip the steps below and exit.
12. If CLKDET# is set (==1), then the codec(s) are Intel® HD Audio.
13. Reassert AC_RESET# bit to put the link back into reset state (NABMBAR at D30:F2:Reg14h
+ offset 2Ch[1]=0).
14. Clear the AC'97 BARs and disable memory/IO space through its PCI register 04h.
15. Hide the AC'97 functions (RCBA+ 3418h[6:5] = 11b)
16. Set the AZ/AC'97# bit to 1 to enable Intel® HD Audio signal mode (D27:F0:Reg40h[0]=1b)
17. Program the Intel® HD Audio AZBAR at PCI config space 10h-17h to a temporary address
and enable it by setting PCI command register 04h[1]=1.
18. De-assert the Controller Reset# bit in Intel® HD Audio to cause the link to start up
(AZBAR+08h [0] = 1)
19. Clear STATESTS bits (AZBAR+0Eh [2:0]) by writing 1s to them.
20. Turn off the link by writing a 0 to the Controller Reset# bit in Intel® HD Audio (AZBAR+08h
[0] = 0). Poll Controller Reset# bit until it reads back as 0.
21. Turn on the link again by writing a 1 to Controller Reset# bit (AZBAR+08h [0] = 1). This
causes a codec link re-enumeration. Wait for about 1 millisecond (ms). Poll Controller Reset#
bit until it reads back as 1.
22. Read the STATESTS bits (AZBAR+0Eh [2:0]) which will indicate which SDIN lines have
codecs on them. If there is one or more bits set to 1, Intel® HD Audio codec(s) are present, go
to step 24. Otherwise there is no codec present.
23. If there is no codec present, BIOS can disable the Intel® HD Audio controller by
Turning off the link by writing a 0 to the Controller Reset bit (AZBAR+08h [0] = 0).
Clearing Intel® HD Audio AZBAR register (offset 10h), then write 0 to PCI command
register at offset 04h.
Disabling Intel® HD Audio controller via Function Disable register (set RCBA+ 3418h[4]
=1).
Skip the following steps and exit.
24. For each Intel® HD Audio codec present as indicated by AZBAR+0Eh[2:0], perform codec
initialization as described in the next section.