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18 Programmer’s Reference Manual
Intel
®
High Definition Audio Controller Registers (D27:F0)
1.1.6 PI—Programming Interface Register
(Intel
®
High Definition Audio Controller—D27:F0)
Offset: 09h Attribute: RO
Default Value: 00h Size: 8 bits
1.1.7 SCC—Sub Class Code Register
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 0Ah Attribute: RO
Default Value: 03h Size: 8 bits
1.1.8 BCC—Base Class Code Register
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 0Bh Attribute: RO
Default Value: 04h Size: 8 bits
1.1.9 CLS—Cache Line Size Register
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 0Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
7:0 Programming Interface — RO.
Bit Description
7:0
Sub Class Code (SCC) — RO.
03h = Audio Device
Bit Description
7:0
Base Class Code (BCC) — RO.
04h = Multimedia device
Bit Description
7:0 Cache Line Size — R/W. Implemented as R/W register, but has no functional impact to the ICH7.