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Programmer’s Reference Manual 23
Intel
®
High Definition Audio Controller Registers (D27:F0)
1.1.20 TCSEL—Traffic Class Select Register
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 44h Attribute: R/W
Default Value: 00h Size: 8 bits
This register assigned the value to be placed in the TC field. CORB and RIRB data will always be
assigned TC0.
Bit Description
7:3 Reserved.
2:0
Intel
®
HIgh Definition Audio Traffic Class Assignment (TCSEL)— R/W. This register assigns the
value to be placed in the Traffic Class field for input data, output data, and buffer descriptor
transactions.
000 = TC0
001 = TC1
010 = TC2
011 = TC3
100 = TC4
101 = TC5
110 = TC6
111 = TC7
NOTE: These bits are not reset on D3
HOT
to D0 transition; however, they are reset by PLTRST#.