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Programmer’s Reference Manual 59
Intel
®
High Definition Audio Controller Registers (D27:F0)
1.2.39 SDLVI—Stream Descriptor Last Valid Index Register
(Intel
®
High Definition Audio Controller—D27:F0)
Memory Address: Input Stream[0]: HDBAR + 8Ch Attribute: R/W
Input Stream[1]: HDBAR + ACh
Input Stream[2]: HDBAR + CCh
Input Stream[3]: HDBAR + ECh
Output Stream[0]: HDBAR + 10Ch
Output Stream[1]: HDBAR + 12Ch
Output Stream[2]: HDBAR + 14Ch
Output Stream[3]: HDBAR + 16Ch
Default Value: 0000h Size: 16 bits
1.2.40 SDFIFOW—Stream Descriptor FIFO Watermark Register
(Intel
®
High Definition Audio Controller—D27:F0)
Memory Address: Input Stream[0]: HDBAR + 8Eh Attribute: R/W
Input Stream[1]: HDBAR + AEh
Input Stream[2]: HDBAR + CEh
Input Stream[3]: HDBAR + EEh
Output Stream[0]: HDBAR + 10Eh
Output Stream[1]: HDBAR + 12Eh
Output Stream[2]: HDBAR + 14Eh
Output Stream[3]: HDBAR + 16Eh
Default Value: 0004h Size: 16 bits
Bit Description
15:8 Reserved.
7:0
Last Valid Index — R/W. The value written to this register indicates the index for the last valid Buffer
Descriptor in BDL. After the controller has processed this descriptor, it will wrap back to the first
descriptor in the list and continue processing.
This field must be at least 1 (i.e., there must be at least 2 valid entries in the buffer descriptor list
before DMA operations can begin).
This value should only be modified when the RUN bit is 0.
Bit Description
15:3 Reserved.
2:0
FIFO Watermark (FIFOW) — R/W. Indicates the minimum number of bytes accumulated/free in the
FIFO before the controller will start a fetch/eviction of data.
010 = 8B
011 = 16B
100 = 32B (Default)
Others = Unsupported
NOTES:
1. When the bit field is programmed to an unsupported size, the hardware sets itself to the default
value.
2. Software must read the bit field to test if the value is supported after setting the bit field.