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64 Programmer’s Reference Manual
AC ’97 Audio Controller Registers (D30:F2)
Core well registers not reset by the D3
HOT
to D0 transition:
• offset 2Ch–2Dh – Subsystem Vendor ID (SVID)
• offset 2Eh–2Fh – Subsystem ID (SID)
• offset 40h – Programmable Codec ID (PCID)
• offset 41h – Configuration (CFG)
Resume well registers will not be reset by the D3
HOT
to D0 transition:
• offset 54h–55h – Power Management Control and Status (PCS)
• Bus Mastering Register: Global Status Register, bits 17:16
• Bus Mastering Register: SDATA_IN MAP register, bits 7:3
2.1.1 VID—Vendor Identification Register (Audio—D30:F2)
Offset: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 Bits
Lockable: No Power Well: Core
2.1.2 DID—Device Identification Register (Audio—D30:F2)
Offset: 02h–03h Attribute: RO
Default Value: See bit description Size: 16 Bits
Lockable: No Power Well: Core
Bit Description
15:0 Vendor ID. This is a 16-bit value assigned to Intel.
Bit Description
15:0
Device ID — RO. This is a 16-bit value assigned to the Intel
®
ICH7 AC ‘97 Audio controller. Refer to
the Intel
®
I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Device ID
Register.