Filter
Top Products
Programmer’s Reference Manual 73
AC ’97 Audio Controller Registers (D30:F2)
2.1.21 PID—PCI Power Management Capability Identification
Register (Audio—D30:F2)
Address Offset: 50h–51h Attribute: RO
Default Value: 0001h Size: 16 bits
Lockable: No Power Well: Core
2.1.22 PC—Power Management Capabilities Register
(Audio—D30:F2)
Address Offset: 52h–53h Attribute: RO
Default Value: C9C2h Size: 16 bits
Lockable: No Power Well: Core
This register is not affected by the D3
HOT
to D0 transition.
Bit Description
15:8 Next Capability (NEXT) — RO. This field indicates that the next item in the list is at offset 00h.
7:0
Capability ID (CAP) — RO.This field indicates that this pointer is a message signaled interrupt
capability
Bit Description
15:11 PME Support — RO. This field indicates PME# can be generated from all D states.
10:9 Reserved.
8:6
Auxiliary Current — RO. This field reports 375 mA maximum suspend well current required when in
the D3
COLD
state.
5
Device Specific Initialization (DSI)—RO. This field indicates that no device-specific initialization is
required.
4 Reserved — RO.
3 PME Clock (PMEC) — RO. This field indicates that PCI clock is not required to generate PME#.
2:0
Version (VER) — RO. This field indicates support for Revision 1.1 of the PCI Power Management
Specification.