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38 Programmer’s Reference Manual
Intel
®
High Definition Audio Controller Registers (D27:F0)
D0h–D1h ISD2FIFOS ISD2 FIFO Size 0077h RO
D2h–D3h ISD2FMT ISD2 Format 0000h R/W
D8h–DBh ISD2BDPL
ISD2 Buffer Descriptor List Pointer-Lower
Base Address
00000000h R/W, RO
DCh–DFh ISD2BDPU
ISD2 Buffer Description List Pointer-Upper
Base Address
00000000h R/W
E0h–E2h ISD3CTL Input Stream Descriptor 3 (ISD3) Control 040000h R/W, RO
E3h ISD3STS ISD3 Status 00h R/WC, RO
E4h–E7h ISD3LPIB ISD3 Link Position in Buffer 00000000h RO
E8h–EBh ISD3CBL ISD3 Cyclic Buffer Length 00000000h R/W
ECh–EDh ISD3LVI ISD3 Last Valid Index 0000h R/W
EEh–EFh ISD3FIFOW ISD3 FIFO Watermark 0004h R/W
F0h–F1h ISD3FIFOS ISD3 FIFO Size 0077h RO
F2h–F3h ISD3FMT ISD3 Format 0000h R/W
F8h–FBh ISD3BDPL
ISD3 Buffer Descriptor List Pointer-Lower
Base Address
00000000h R/W, RO
FCh–FFh ISD3BDPU
ISD3 Buffer Description List Pointer-Upper
Base Address
00000000h R/W
100h–102h OSD0CTL Output Stream Descriptor 0 (OSD0) Control 040000h R/W, RO
103h OSD0STS OSD0 Status 00h R/WC, RO
104h–107h OSD0LPIB OSD0 Link Position in Buffer 00000000h RO
108h–10Bh OSD0CBL OSD0 Cyclic Buffer Length 00000000h R/W
10Ch–10Dh OSD0LVI OSD0 Last Valid Index 0000h R/W
10Eh–10Fh OSD0FIFOW OSD0 FIFO Watermark 0004h R/W
110h–111h OSD0FIFOS OSD0 FIFO Size 00BFh R/W
112–113h OSD0FMT OSD0 Format 0000h R/W
118h–11Bh OSD0BDPL
OSD0 Buffer Descriptor List Pointer-Lower
Base Address
00000000h R/W, RO
11Ch–11Fh OSD0BDPU
OSD0 Buffer Description List Pointer-Upper
Base Address
00000000h R/W
120h–122h OSD1CTL Output Stream Descriptor 1 (OSD1) Control 040000h R/W, RO
123h OSD1STS OSD1 Status 00h R/WC, RO
124h–127h OSD1LPIB OSD1 Link Position in Buffer 00000000h RO
128h–12Bh OSD1CBL OSD1 Cyclic Buffer Length 00000000h R/W
12Ch–12Dh OSD1LVI OSD1 Last Valid Index 0000h R/W
12Eh–12Fh OSD1FIFOW OSD1 FIFO Watermark 0004h R/W
130h–131h OSD1FIFOS OSD1 FIFO Size 00BFh R/W
132h–133h OSD1FMT OSD1 Format 0000h R/W
Table 1-2. Intel
®
High Definition Audio PCI Register Address Map
(Intel
®
High Definition Audio D27:F0) (Sheet 3 of 4)
HDBAR +
Offset
Mnemonic Register Name Default Access